A Novel Design Methodology for Error-Resilient Circuits in Near-Threshold Computing

Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads.