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Extreme Low Power Technology Using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

Date
2020/11/09
Published in
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Author
Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, Byoung Hun Lee
Type
International Conference