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International Journal (SCIE)
10
An Area and Power Efficient Ternary Serial Adder Using Phase Composite ZnO Stack Channel FETs
2025/04/08
Nanoscale Advances
Trends and Challenges in Computing-in-memory for Neural Network Model: A Review from Device Design to Application-side Optimization
2024/12/04
IEEE ACCESS
Configurable Anti-Ambipolar Photoresponses for Optoelectronic Multi-Valued Logic Gates
2024/07/30
Applied Physics Letters
Junctionless Negative-Differential-Resistance Device using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing
2024/03/07
Advanced Materials
Optimizing Ternary Multiplier Design with Fast Ternary Adder
2022/09/20
IEEE Transactions on Circuits and Systems II: Express Briefs
Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
2022/06/28
ACS Nano
Low-power Ternary Multiplication Using Approximate Computing
2021/03/26
IEEE Transactions on Circuits and Systems II: Express Briefs
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
2020/05/07
IEEE Transactions on Circuits and Systems I: Regular Papers
Tunneling-based Ternary Metal-Oxide-Semiconductor Technology
2019/07/15
Nature Electronics
Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
2018/10/05
IEEE Electron Device Letters
International Conference
13
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor
2022/03/14
IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE)
Memcapacitor based Minimum and Maximum Gate Design
2021/10/06
IEEE International SoC Design Conference (ISOCC)
Ternary Sense Amplifier Design for Ternary SRAM
2021/10/06
IEEE International SoC Design Conference (ISOCC)
Design and Analysis of a Low-Power Ternary SRAM
2021/05/22
IEEE International Symposium on Circuits and Systems (ISCAS)
Extreme Low Power Technology Using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction
2020/11/09
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
MTCMOS-based Ternary to Binary Converter
2020/10/21
IEEE International SoC Design Conference (ISOCC)
Low-power 4-trit Current-steering DAC for Ternary Data Conversion
2020/10/21
IEEE International SoC Design Conference (ISOCC)
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU
2019/10/06
IEEE International SoC Design Conference (ISOCC)
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm
2019/05/21
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
2019/05/21
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
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