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International Journal (SCIE)
17
Reconfigurable CMOS ternary inverter based on charge-trapping-enabled VTC modulation
2026/09/22
Scientific Reports
A16K: 1.6 nm Technology Libraries and LLE-Aware Chip-Level Timing Prediction
2026/09/07
IEEE Transactions on Circuits and Systems I: Regular Papers
BO–RL Hybrid Framework for a-IGZO TFT Compact Model Parameter Extraction in 2T0C DRAM Applications
2026/08/25
Advanced Intelligent Systems
4-Transistor IGZO Ternary Content Addressable Memory Enabling Large-Scale Array Integration for In-Memory Computing
2026/08/21
IEEE Electron Device Letters
A Ternary Hybrid Perceptron Branch Predictor for Ternary Pipelined Architectures
2026/08/07
IEEE Access
LW-ResGRU DPD: Layer-Wise Residual GRU for Low-Latency DPD in Nonlinear RF Systems
2025/12/05
IEEE Transactions on Circuits and Systems II: Express Briefs
An RTL-based General Synthesis Methodology for Device-Independent Ternary Logic Circuits
2025/09/16
IEEE Access
An Area and Power Efficient Ternary Serial Adder Using Phase Composite ZnO Stack Channel FETs
2025/04/08
Nanoscale Advances
Trends and Challenges in Computing-in-memory for Neural Network Model: A Review from Device Design to Application-side Optimization
2024/12/04
IEEE Access
Configurable Anti-Ambipolar Photoresponses for Optoelectronic Multi-Valued Logic Gates
2024/07/30
Applied Physics Letters
Junctionless Negative-Differential-Resistance Device using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing
2024/03/07
Advanced Materials
Optimizing Ternary Multiplier Design with Fast Ternary Adder
2022/09/20
IEEE Transactions on Circuits and Systems II: Express Briefs
Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
2022/06/28
ACS Nano
Low-power Ternary Multiplication Using Approximate Computing
2021/03/26
IEEE Transactions on Circuits and Systems II: Express Briefs
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
2020/05/07
IEEE Transactions on Circuits and Systems I: Regular Papers
Tunneling-based Ternary Metal-Oxide-Semiconductor Technology
2019/07/15
Nature Electronics
Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors
2018/10/05
IEEE Electron Device Letters
International Journal (SCOPUS)
3
Novel Design of 8T Ternary SRAM for Low Power Sensor System
2023/05/31
Journal of Sensor Science and Technology
Energy-Efficient Ternary Modulator for Wireless Sensor Networks
2023/05/31
Journal of Sensor Science and Technology
Area-and Energy-Efficient Ternary D Flip-Flop Design
2023/05/31
Journal of Sensor Science and Technology
International Conference
14
A16K: 1.6nm NSFET, FSFET, and CFET Technology Libraries for Chip-Level VLSI Prediction
2026/06/18
IEEE International Symposium on Circuits and Systems (ISCAS)
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor
2022/03/14
IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE)
Memcapacitor based Minimum and Maximum Gate Design
2021/10/06
IEEE International SoC Design Conference (ISOCC)
Ternary Sense Amplifier Design for Ternary SRAM
2021/10/06
IEEE International SoC Design Conference (ISOCC)
Design and Analysis of a Low-Power Ternary SRAM
2021/05/22
IEEE International Symposium on Circuits and Systems (ISCAS)
Extreme Low Power Technology Using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction
2020/11/09
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
MTCMOS-based Ternary to Binary Converter
2020/10/21
IEEE International SoC Design Conference (ISOCC)
Low-power 4-trit Current-steering DAC for Ternary Data Conversion
2020/10/21
IEEE International SoC Design Conference (ISOCC)
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU
2019/10/06
IEEE International SoC Design Conference (ISOCC)
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm
2019/05/21
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
2019/05/21
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
An Optimal Gate Design for the Synthesis of Ternary Logic Circuits
2018/01/22
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
A Novel Ternary Multiplier based on Ternary CMOS Compact Model
2017/05/22
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
A Novel Design Methodology for Error-Resilient Circuits in Near-Threshold Computing
2016/10/26
IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)