Publications

Advanced Materials, one of the world's most prestigious journals, is the home of choice for best-in-class materials science for more than 30 years.

Existing ternary multiplier designs are difficult to use in ternary systems. Thus, ternary Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders are proposed to improve the performance of existing ternary multipliers. A ternary carry-select adder is also proposed to reduce the carry propagation delay, used as a carry-chain adder of the Wallace tree.

We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and 2 ×2 ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient 6 ×6 approximate ternary multipliers.

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value.

The power density limits of complementary metal-oxide-semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology.

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10 -16 J, which is comparable to the binary equivalent circuit.

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of V_DD/2 and V_DD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when V_DD is set to 0.9 V.

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes.

In this paper, we suggest a new structure of complementary capacitive switch that is composed of two connected memcapacitors. We also propose MIN and MAX gates that use this structure. HSPICE simulation verified the behavior of these logic gates for a specific input pattern.

This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-to-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size.

This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89μA to 1.46μA.

Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect portion. We examined the benefits of ternary logic including the impacts of interconnect length reduction using a realistic ternary device model.

Ternary logic circuits can reduce circuit power consumption and interconnections. We propose a ternary to binary converter that uses multi-threshold CMOS (MTCMOS) for energy-efficient logic converting to use these benefits. We reduce the delay by 8.61%, power by 28.72 % compared to the previous design.

A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology.

Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor.

Logic synthesis has been increasingly important to accelerate the development of high-level systems. However, in multi-valued logic, logic synthesis methods that can process emerging devices are deficient. We propose and automate a method to synthesize ternary logic circuits. Our design of ternary logic circuits is based on static gate design, and exploits carbon nanotube field-effect transistors.

We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed ci r cuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate.