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2025 first half
26
HiPPO: Recurrent Memory with Optimal Polynomial Projections
Part of Advances in Neural Information Processing Systems 33 (NeurIPS 2020)
HiPPO: Recurrent Memory with Optimal Polynomial Projections
Advances in neural information processing systems (2020)
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An energy-efficient switching scheme based on a splitting structure
Microelectronics Journal (2023)
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A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs
IEEE Transactions on Circuits and Systems I: Regular Papers (2022)
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A 0.021μm² High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery
IEEE International Solid-State Circuits Conference (2025)
OPAL: Outlier-Preserved Microscaling Quantization Accelerator for Generative Large Language Models | Proceedings of the 61st ACM/IEEE Design Automation Conference
Transformer-based large language models (LLMs) have achieved great success with the growing model size. LLMs' size grows by 240× every two years, which outpaces the hardware progress and makes model inference increasingly costly. Model quantization is ...
OPAL:Outlier-Preserved Microscaling Quantization Accelerator for Generative Large Language Models
IEEE/ACM Design Automation Conference (DAC), (2024)
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A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction
IEEE Transactions on Circuits and Systems II: Express Briefs (2020)
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RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2025)
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An Enhanced Folded Cascode OTA with push pull Input Stage
International Multi-Conference on Systems, Signals & Devices (2012)
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DIET-PIM: Dynamic Importance-based Early Termination for Energy-Efficient Processing-in-Memory Accelerator
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (2024)
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PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems
57th IEEE/ACM International Symposium on Microarchitecture (MICRO) (2024)
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2024 second half
42
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High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm
IEEE Transactions on Circuits and Systems I: Regular Papers (2024)
DPD-NeuralEngine: A 22-nm 6.6-TOPS/W/mm$^2$ Recurrent Neural...
The increasing adoption of Deep Neural Network (DNN)-based Digital Pre-distortion (DPD) in modern communication systems necessitates efficient hardware implementations. This paper presents...
DPD-NeuralEngine: A 22-nm 6.6-TOPS/W/mm2 Recurrent Neural Network Accelerator for Wideband Power Amplifier Digital Pre-Distortion
arXiv, Hardware Architecture (2024)
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Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-algorithm
IEEE International Symposium on Multiple-Valued Logic (2000)
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Analyzing and Improving the Image Quality of StyleGAN
IEEE/CVF Conference on Computer Vision and Pattern Recognition (2020)
DNA-based programmable gate arrays for general-purpose DNA computing
Nature - Generic single-stranded oligonucleotides used as a uniform transmission signal can reliably integrate large-scale DNA integrated circuits with minimal leakage and high fidelity for...
DNA-based programmable gate arrays for general-purpose DNA computing
Nature (2023)
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A 1Tb 4b/Cell 64-Stacked-WL 3D NAND Flash Memory with 12MB/s Program Throughput
IEEE International Solid-State Circuits Conference (2018)
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A high speed pseudo-random bit generator driven by 2D-discrete hyperchaos
Chaos, Solitons & Fractals (2023)
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TPCSA-MRAM: Ternary Precharge Sense Amplifier-Based MRAM
IEEE Access (2024)
Tunnelling-based ternary metal–oxide–semiconductor technology
Nature Electronics - Quantum-mechanical band-to-band tunnelling can be used to create an energy-efficient ternary logic technology that can be fabricated on the wafer scale using complementary...
Tunnelling-based ternary metal–oxide–semiconductor technology
Nature Electronics (2019)
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Machine Learning Approaches in Battery Management Systems: State of the Art
IEEE International Conference on Industrial Electronics for Sustainable Energy Systems (2020)
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2024 first half
50
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Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning
IEEE Micro (2019)
ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory based SSDs | MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture
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ParaBit: Processing Parallel Bitwise Operations in NAND Flash
IEEE/ACM International Symposium on Microarchitecture (2021)
Third Base
Three cheers for base 3!
Third Base
American Scientist (2001)
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BTC-Net: Efficient Bit-Level Tensor Data Compression Network for Hyperspectral Image
IEEE Transactions on Geoscience and Remote Sensing (2024)
Growth of diamond in liquid metal at 1 atm pressure
Nature - Diamond crystals and polycrystalline diamond films can be grown using liquid metal at standard pressure and high temperature instead of conventional high pressure and high temperature.
Growth of diamond in liquid metal at 1 atm pressure
Nature (2024)
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Demystifying Emerging Nonvolatile Memory Technologies: Understanding Advantages, Challenges, Trends, and Novel Applications
IEEE International Symposium on Circuits and Systems (2019)
CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors
Nature Electronics - A 1 Mb non-volatile computing-in-memory system, which integrates a resistive memory array with control and readout circuits using an established 65 nm foundry CMOS...
CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors
Nature Electronics (2019)
Memcapacitive Devices in Logic and Crossbar Applications
Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and...
Memcapacitive Devices in Logic and Crossbar Applications
arXiv, Emerging Technologies (2017)
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Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis
IEEE Transactions on Circuits and Systems II: Express Briefs (2022)
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An Asymmetric SRAM cell to lower Gate Leakage
International Symposium on Signals, Circuits and Systems. Proceedings (2003)
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2023 second half
46
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High-performance SRAM in nanoscale CMOS: Design challenges and techniques
IEEE International Workshop on Memory Technology, Design and Testing (2007)
Standard cell sizing for subthreshold operation | Proceedings of the 49th Annual Design Automation Conference
Technische Univ. Eindhoven, Eindhoven, NL, and Holst Centre/imec-nl, Eindhoven, NL
Standard cell sizing for subthreshold operation
IEEE/ACM Design Automation Conference (2012)
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Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer
IEEE Micro (2022)
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CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
IEEE Transactions on Nanotechnology (2011)
A full spectrum of computing-in-memory technologies
Nature Electronics - This Review provides a full-spectrum classification of computing-in-memory technologies by identifying the degree of memory cells participating in the computation as inputs...
A full spectrum of computing-in-memory technologies
Nature Electronics (2023)
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Design of CNFET based ternary comparator using grouping logic
IEEE Faible Tension Faible Consommation (2012)
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Novel 2.5D RDL Interposer Packaging: A Key Enabler for the New Era of Heterogenous Chip Integration
IEEE Electronic Components and Technology Conference (2021)
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Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator
IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (2021)
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Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product
IEEE/ACM Annual International Symposium on Computer Architecture (2021)
Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron
This paper presents a performance comparison of a carbon nanotube-based field effect (CNFET)- and CMOS-based 6T SRAM cell at the 32nm technology node.…
Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron
Microelectronics Journal (2009)
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2023 first half
6
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XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks
IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (2018)
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XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
IEEE Journal of Solid-State Circuits (2020)
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Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
IEEE Journal of Solid-State Circuits (2017)
Modern microprocessor built from complementary carbon nanotube transistors
Nature - A 16-bit microprocessor built from over 14,000 carbon nanotube transistors may enable energy efficiency advances in electronics technologies beyond silicon.
Modern microprocessor built from complementary carbon nanotube transistors
Nature (2019)
Carbon nanotube computer
Nature - Carbon nanotubes have long been touted as promising building blocks for computers based on carbon rather than silicon. A main motivation towards this goal is the potential for circuits...
Carbon nanotube computer
Nature (2013)
Tunnelling-based ternary metal-oxide-semiconductor technology - Nature Electronics
The power density limits of complementary metal-oxide-semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology.
Tunnelling-based ternary metal–oxide–semiconductor technology
Nature Electronics (2019)
