Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU

Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor.