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Ternary Sense Amplifier Design for Ternary SRAM

Date
2021/10/06
Published in
IEEE International SoC Design Conference (ISOCC)
Author
Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang
Type
International Conference
Ternary Sense Amplifier Design for Ternary SRAM
This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-to-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size.
https://ieeexplore.ieee.org/abstract/document/9613911