Low-power Ternary Multiplication Using Approximate Computing

We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and 2 ×2 ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient 6 ×6 approximate ternary multipliers.